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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14538B Dual Precision Retriggerable/Resettable Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an accurate output pulse over a wide range of widths, the duration and accuracy of which are determined by the external timing components, CX and RX. * Unlimited Rise and Fall Time Allowed on the A Trigger Input * Pulse Width Range = 10 s to 10 s * Latched Trigger Inputs * Separate Latched Reset Inputs * 3.0 Vdc to 18 Vdc Operational Limits * Triggerable from Positive (A Input) or Negative-Going Edge (B-Input) * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range * Pin-for-pin Compatible with MC14528B and CD4528B (CD4098) * Use the MC54/74HC4538A for Pulse Widths Less Than 10 s with Supplies Up to 6 V. MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
DW SUFFIX SOIC CASE 751G
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL *MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
Value Unit V V - 0.5 to + 18.0 Vin, Vout Iin, Iout PD Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 10 500 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg TL - 65 to + 150 260
BLOCK DIAGRAM
CX RX 2 Q1 5 B Q1 RESET 3 CX 15 14 Q2 B Q2 RESET 13 RX AND CX ARE EXTERNAL COMPONENTS. VDD = PIN 16 VSS = PIN 8, PIN 1, PIN 15 * Consult factory for possible "D" suffix SOIC Case 751B. 10 9 RX 6 7 VDD
1 4 A
_C _C
Lead Temperature (8-Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
VDD
ONE-SHOT SELECTION GUIDE
100 ns MC14528B MC14536B MC14538B MC14541B MC4538A* *LIMITED OPERATING VOLTAGE (2 - 6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE 1 s 10 s 100 s 1 ms 10 ms 100 ms 1s 10 s 23 HR 5 MIN.
12 11
A
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14538B 1
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 15 -- -- 5.0 10 15 5.0 10 15 5.0 10 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.05 0.1 -- -- 5.0 10 20 2.0 2.0 2.0 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 0.00001 25 5.0 0.005 0.010 0.015 0.04 0.08 0.13 -- -- -- -- -- -- -- 0.05 0.1 -- 7.5 5.0 10 20 0.20 0.45 0.70 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 1.0 -- -- 150 300 600 2.0 2.0 2.0 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current, Pin 2 or 14 Input Current, Other Inputs Input Capacitance, Pin 2 or 14 Input Capacitance, Other Inputs (Vin = 0) Quiescent Current (Per Package) Q = Low, Q = High Quiescent Current, Active State (Both) (Per Package) Q = High, Q = Low **Total Supply Current at an external load capacitance (CL) and at external timing network (RX, CX) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Iin Cin Cin IDD Adc Adc pF pF Adc IDD mAdc IT IT = (3.5 x 10-2) RXCXf + 4CXf + 1 x 10-5 CLf IT = (8.0 x 10-2) RXCXf + 9CXf + 2 x 10-5 CLf IT = (1.25 x 10-1) RXCXf + 12CXf + 3 x 10-5 CLf where: IT in A (one monostable switching only), where: CX in F, CL in pF, RX in k ohms, and where: f in Hz is the input frequency. Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14538B 2
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 tTHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 tr, tf 5 10 15 5 10 15 5 10 15 tWH, tWL trr 5.0 10 15 5.0 10 15 170 90 80 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- 300 150 100 250 125 95 -- -- -- 300 1.2 0.4 No Limit 85 45 40 -- -- -- -- -- -- -- -- -- ns 600 300 220 ns 500 250 190 15 5 4 1.0 0.1 0.05 s -- -- -- 100 50 40 200 100 80 ns All Types Typ # 100 50 40 Min -- -- -- Max 200 100 80 ns Unit ns Output Rise Time tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/pF) CL + 20 ns Output Fall Time tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns Propagation Delay Time A or B to Q or Q tPLH, tPHL = (0.90 ns/pF) CL + 255 ns tPLH, tPHL = (0.36 ns/pF) CL + 132 ns tPLH, tPHL = (0.26 ns/pF) CL + 87 ns Reset to Q or Q tPLH, tPHL = (0.90 ns/pF) CL + 205 ns tPLH, tPHL = (0.36 ns/pF) CL + 107 ns tPLH, tPHL = (0.26 ns/pF) CL + 82 ns Input Rise and Fall Times Reset B Input ms A Input -- Input Pulse Width A, B, or Reset Retrigger Time ns Output Pulse Width -- Q or Q Refer to Figures 8 and 9 CX = 0.002 F, RX = 100 k T 5.0 10 15 5.0 10 15 5.0 10 15 100 [(T1 - T2)/T1] 5.0 10 15 198 200 202 9.3 9.4 9.5 0.91 0.92 0.93 -- -- -- 210 212 214 9.86 10 10.14 0.965 0.98 0.99 1.0 1.0 1.0 230 232 234 10.5 10.6 10.7 1.03 1.04 1.06 5.0 5.0 5.0 ms s CX = 0.1 F, RX = 100 k CX = 10 F, RX = 100 k s
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
Pulse Width Match between circuits in the same package. CX = 0.1 F, RX = 100 k
%
OPERATING CONDITIONS
External Timing Resistance
RX CX
-- --
5.0 0
-- --
k F
External Timing Capacitance
No Limit
* The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 M.. If CX > 15 F, use discharge protection diode per Fig. 11.
MOTOROLA CMOS LOGIC DATA
MC14538B 3
VDD RX 2 (14) CX
VDD P1 ENABLE + C2 -
1 (15) N1 4 (12) 5 (11) B RESET 3 (13) VSS
Vref1
+ C1 -
ENABLE
Vref2
R Q OUTPUT LATCH S Q
6 (10) 7 (9)
CONTROL
A
QR S
RESET LATCH
QR R
NOTE: Pins 1, 8 and 15 must be externally grounded
Figure 1. Logic Diagram (1/2 of DevIce Shown)
VDD 500 pF ID RX VSS Vin CX CX/RX Q Q Q Q CL VSS CL CL Vin CL 20 ns 90% 10% 20 ns VDD 0V 0.1 F CERAMIC RX CX
VSS
A B RESET A B
RESET
Figure 2. Power Dissipation Test Circuit and Waveforms
VDD
INPUT CONNECTIONS
RX VSS PULSE GENERATOR PULSE GENERATOR PULSE GENERATOR CX CX/RX Q Q Q Q CL VSS CL CL CL RX CX * CL = 50 pF VSS Characteristics tPLH, tPHL, tTLH, tTHL, T, tWH, tWL tPLH, tPHL, tTLH, tTHL, T, tWH, tWL tPLH(R), tPHL(R), tWH, tWL * Includes capacitance of probes, wiring, and fixture parasitic. NOTE: Switching test waveforms for PG1, PG2, PG3 are shown In Figure 4. Reset VDD VDD PG3 A PG1 VSS PG1 B VDD PG2 PG2
A B RESET A B
PG1 = PG2 = PG3 =
RESET
Figure 3. Switching Test Circuit
MC14538B 4
MOTOROLA CMOS LOGIC DATA
50% A tWH B 50% tWL RESET tTHL 90% 10% tTLH 90% 10% tTHL tTLH
90% 10% tTHL tTHL 90% 10% tTHL 90% 10% tPHL 50% tWL tPHL tTLH
50%
VDD
VDD
VDD
tPLH 50% Q
T 50% tPHL
tPLH 50%
tTLH
trr 50%
tPHL Q 50%
tPLH 50% 50%
50%
Figure 4. Switching Test Waveforms
TA = 25C RX = 100 k CX = 0.1 F 1.0 0.8 0.6 0.4 0.2 0
0% POINT PULSE WIDTH VDD = 5.0 V, T = 9.8 ms VDD = 10 V, T = 10 ms VDD = 15 V, T = 10.2 ms
NORMALIZED PULSE WIDTH CHANGE WITH RESPECT TO VALUE AT VDD = 10 V (%)
RELATIVE FREQUENCY OF OCCURRENCE
2 1 0 1 2
RX = 100 k CX = 0.1 F
-4 -2 0 2 4 T, OUTPUT PULSE WIDTH (%)
5
6
7
8 9 10 11 12 VDD, SUPPLY VOLTAGE (VOLTS)
13
14
15
Figure 5. Typical Normalized Distribution of Units for Output Pulse Width
Figure 6. Typical Pulse Width Variation as a Function of Supply Voltage VDD
1000 TOTAL SUPPLY CURRENT ( A) RX = 100 k, CL = 50 pF ONE MONOSTABLE SWITCHING ONLY
FUNCTION TABLE
Inputs Reset H H 5.0 V 10 V H H H H L A L L H L, H, L X X H L, H, X X Not Triggered Not Triggered Not Triggered Not Triggered L H Not Triggered B H Q Outputs Q
100
VDD = 15 V 10
1.0
0.1 0.001
0.1
1.0 OUTPUT DUTY CYCLE (%)
10
100
Figure 7. Typical Total Supply Current versus Output Duty Cycle
MOTOROLA CMOS LOGIC DATA
MC14538B 5
TYPICAL NORMALIZED ERROR WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)
TYPICAL NORMALIZED ERROR WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)
2 1 0 -1 -2
RX = 100 k CX = 0.1 F
3.0 2.0 1.0 0 VDD = 15 V VDD = 10 V
RX = 100 k CX = .002 F
VDD = 15 V VDD = 10 V VDD = 5 V
- 1.0 - 2.0
- 3.0
VDD = 5.0 V
- 60 - 40
- 20
0 20 40 60 80 100 TA, AMBIENT TEMPERATURE (C)
120
140
- 60 - 40
- 20
0 20 40 60 80 100 TA, AMBIENT TEMPERATURE (C)
120
140
Figure 8. Typical Error of Pulse Width Equation versus Temperature
Figure 9. Typical Error of Pulse Width Equation versus Temperature
THEORY OF OPERATION
1 3 4
A
2
B
5
RESET Vref 2 CX/RX Vref 1 Vref 1 Vref 2 Vref 1 Vref 2 Vref 1 Vref 2
Q T
1 2 3
T Positive edge trigger Negative edge trigger Positive edge trigger
4 5
T Positive edge re-trigger (pulse lengthening) Positive edge re-trigger (pulse lengthening)
Figure 10. Timing Operation
TRIGGER OPERATION The block diagram of the MC14538B is shown in Figure 1, with circuit operation following. As shown in Figure 1 and 10, before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor CX completely charged to V DD. When the trigger input A goes from V SS to V DD (while inputs B and Reset are held to V DD) a valid trigger is recognized, which turns on comparator C1 and N-channel transistor N1 . At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward V SS until V ref1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time MC14538B 6
comparator C2 turns on. With transistor N1 off, the capacitor CX begins to charge through the timing resistor, R X, toward V DD. When the voltage across CX equals Vref 2, comparator C2 changes state, causing the output latch to reset (Q goes low) while at the same time disabling comparator C2 . This ends at the timing cycle with the monostable in the quiescent state, waiting for the next trigger. In the quiescent state, CX is fully charged to VDD causing the current through resistor RX to be zero. Both comparators are "off" with total device current due only to reverse junction leakages. An added feature of the MC14538B is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CX, RX, or the duty cycle of the input waveform. MOTOROLA CMOS LOGIC DATA
RETRIGGER OPERATION The MC14538B is retriggered if a valid trigger occurs followed by another valid trigger before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from Vref 1, but has not yet reached Vref 2, will cause an increase in output pulse width T. When a valid retrigger is initiated , the voltage at C X /R X will again drop to V ref 1 before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger. RESET OPERATION The MC14538B may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on Reset sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor P1 . When the voltage on the capacitor reaches Vref 2, the reset latch will clear, and will then be ready to accept another pulse. It the Reset input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level is detected on the Reset input, the output pulse T can be made significantly shorter than the minimum pulse width specification. POWER-DOWN CONSIDERATIONS Large capacitance values can cause problems due to the large amount of energy stored. When a system containing the MC14538B is powered down, the capacitor voltage may discharge from V DD through the standard protection diodes at pin 2 or 14. Current through the protection diodes should be limited to 10 mA and therefore the discharge time of the V DD supply must not be faster than (V DD). (C)/ (10 mA). For example, if V DD = 10 V and CX = 10 F, the V DD supply should discharge no faster than (10 V) x (10 F) / (10 mA) = 10 ms. This is normally not a problem since power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of V DD to zero volts occurs, the MC14538B can sustain damage. To avoid this possibility use an external clamping diode, D X, connected as shown in Fig. 11.
Dx
PIN ASSIGNMENT
Cx VSS Rx VDD VDD Q Q RESET VSS CX/RXA RESET A AA BA QA QA VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VSS CX/RXB RESET B AB BB QB QB
Figure 11. Use of a Diode to Limit Power Down Current Surge
MOTOROLA CMOS LOGIC DATA
MC14538B 7
TYPICAL APPLICATIONS
CX CX RX VDD RISING-EDGE A TRIGGER B B = VDD RESET = VDD CX A = VSS RX VDD Q B FALLING-EDGE TRIGGER RESET = VDD Q FALLING-EDGE TRIGGER RESET = VDD A B Q Q Q RESET = VDD CX RX VDD Q RISING-EDGE A TRIGGER B RX VDD Q Q
Figure 12. Retriggerable Monostables Circuitry
Figure 13. Non-Retriggerable Monostables Circuitry
NC Q Q CD VDD VDD NC NC
A B
Figure 14. Connection of Unused Sections
MC14538B 8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14538B 9
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 _ C -T-
14X DIM A B C D F G J K M P R
G
K
SEATING PLANE
M
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MC14538B 10
*MC14538B/D*
MOTOROLA CMOS LOGIC DATA MC14538B/D

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